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GATE Computer Science (CS) 2018 Shift 1 Solved Paper

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Question : 53 of 65

Marks: +1, -0

The instruction pipeline of a RISC processor has the following stages. Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Writeback (WB). The IF, ID, OF and WB stages take 1 clock cycle each for every instruction. Consider a sequence of 100 instructions. In the PO stage, 40 instructions take 3 clock cycles each, 35 instructions take 2 clock cycles each, and the remaining 25 instructions take 1 clock cycle each. assume that there are no data hazards and no control hazards. The number of clock cycles required for completion of execution of the sequence of instructions is ____________.

Your Answer:

Solution:

	IF	ID	OF	PO	WB
Type $(f_1)$	1	1	1	3	1
Type $(f_2)$	1	1	1	2	1
Type $(f_3)$	1	1	1	1	1

I_{1}: 1+1+1+3+1=7

\begin{array}{c c} I_2 & : \\ I_3 & : \end{array}

usually takes cycles each due to overlapping but

I_1

(PO) takes 2 cycles to add “1” cycle extra (2 + 1)

\Rightarrow 7+8+1=10

	1	2	3	4	5	6	7	8	9	10
$I_1$	IF	ID	OF	PO	PO	PO	WB
$I_2$		IF	ID	OF	OF	OF	PO	PO	WB
$I_3$			IF	ID	ID	ID	OF	OF	PO	PO

	IF	ID	OF	PO	WB
$I_1$	1	1	1	3	1
$I_2$	1	1	1	3	1
$I_3$	1	1	1	2	1
$I_4$	1	1	1	2	1
$I_5$	1	1	1	1	1
$I_6$	1	1	1	1	1

If Type 1 – 2 instruction

Type 2 – 2 instruction

Type 3 – 2 instruction

I:: 1+1+1+3+1=7

I_{2}: 1+2

extra cycle

=3

I_{3}: 1+1

extra cycle

=2

I_{4}: 1+1

extra cycle

=2

I_{5}: 1

extra cycle

=1

I_{6}: 1

extra cycle

=1

=16

In this way, if we compute 100 instruction number of cycles required is If ID OF PO WB

\Rightarrow 1+1+1+[(40 \times 3)+(35 \times 2)+(25 \times 1)]+1

\Rightarrow 219

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