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GATE Computer Science (CS) 2020 Solved Papers

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Question : 50 of 65

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Consider a non-pipelined processor operating at 2.5 GHz. It takes 5 clock cycles to complete an instruction. You are going to make a 5-stage pipeline out of this processor. Overheads associated with pipelining force you to operate the pipeline processor at 2 GHz. In a given program, assume that 30% are memory instructions, 60% are ALU instructions and the rest are branch instruction. 5% of the memory instructions cause stalls of 50 clock cycles each due to cache misses and 50% of the branch instructions cause stalls of 2 cycles each. Assume that there are no stalls associated with the execution of ALU instructions. For this program, the speedup achieved by the pipelined processor over the non-pipeline processor (round off to 2 decimal places) is ______.

Your Answer:

Solution:

Non-pipeline

Clock frequency

=2.5\text{ GHz}

Cycle time

=\frac{1}{2.5\text{ GHz}}=0.4\text{ ns}

Given,

\text{CPI}=5

So, ET

_{\text{non-pipe}}=\text{CPI}\times

Cycle time

=5\times 0.4\text{ ns}=2\text{ ns}

Pipeline:

Clock frequency

=24\text{ GHz}

Cycle time

=\frac{1}{2\text{ GHz}}=0.5\text{ ns}

\therefore

Number of stalls/instruction

=0.3\times 0.05\times 50+0.1\times 0.5\times 2

=0.85

Avg. instruction

\text{ET}_{\text{pipe}}=(1+

No. of stall instruction)

^{*}

cycle time

=(1+0.85)\times 0.5\text{ ns}=0.925\text{ ns}

\text{S}=\frac{\text{ET}_{\text{non-pipe}}}{\text{ET}_{\text{pipe}}}=\frac{2}{0.925}=2.16

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