Statement 1: True, Daisy chaining assign non-uniform priorities in attending interrupts. Statement 2: False, A vectored interrupt means, CPU knows the source of the interrupt. Statement 3: True, polling technique makes CPU to periodically verity states bits and service for need Statement 4: False: During DMA also, CPU will have master control over the bus. (OR) IOP (I/O processor) and CPU can be mastered but not at the same time. Hence, I and III are true