A 1 to 8 demultiplexer with data input D_in, address inputs S₀, S₁, and S₂, (with S₀ as the LSB) and Y̅₀ to Y̅ ₇ as the eight de-multiplexed output, is to be designed using two 2 to 4 decoders (with enable input E and address input A₀ and A₁) as shown in the figure. D_in, S₀, S₁, and S₂ are to be connected to P, Q, R, and S but not necessarily in this order. The respective input connections to P, Q, R, and S terminals should be

Question

Examsnet · Accepted Answer

Correct Answer is : Din, S2, S0, and S1

GATE Electronics and Communications (EC) 2015 Shift 2 Solved Paper