Examsnet
Unconfined exams practice
Home
Exams
Banking Entrance Exams
CUET Exam Papers
Defence Exams
Engineering Exams
Finance Entrance Exams
GATE Exam Practice
Insurance Exams
International Exams
JEE Exams
LAW Entrance Exams
MBA Entrance Exams
MCA Entrance Exams
Medical Entrance Exams
Other Entrance Exams
Police Exams
Public Service Commission (PSC)
RRB Entrance Exams
SSC Exams
State Govt Exams
Subjectwise Practice
Teacher Exams
SET Exams(State Eligibility Test)
UPSC Entrance Exams
Aptitude
Algebra and Higher Mathematics
Arithmetic
Commercial Mathematics
Data Based Mathematics
Geometry and Mensuration
Number System and Numeracy
Problem Solving
Board Exams
Andhra
Bihar
CBSE
Gujarat
Haryana
ICSE
Jammu and Kashmir
Karnataka
Kerala
Madhya Pradesh
Maharashtra
Odisha
Tamil Nadu
Telangana
Uttar Pradesh
English
Competitive English
Certifications
Technical
Cloud Tech Certifications
Security Tech Certifications
Management
IT Infrastructure
More
About
Careers
Contact Us
Our Apps
Privacy
Test Index
GATE Electronics and Communications (EC) 2022 Solved Paper
Show Para
Hide Para
Share question:
© examsnet.com
Question : 18
Total: 65
Consider the CMOS circuit shown in the figure (substrates are connected to their respective sources). The gate width (W) to gate length (L) ratios
(
W
L
)
of the transistors are as shown. Both the transistors have the same gate oxide capacitance per unit area. For the pMOSFET, the threshold voltage is -1 V and the mobility of holes is 40
c
m
2
V
.
s
. For the nMOSFET, the threshold voltage is 1 V and the mobility of electrons is 300
c
m
2
V
.
s
The steady state output voltage V
0
is _________.
equal to 0 V
more than 2 V
less than 2 V
equal to 2 V
Validate
Solution:
© examsnet.com
Go to Question:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
Prev Question
Next Question